1. Field of the Invention
This invention generally relates to integrated circuit (IC) and liquid crystal display (LCD) fabrication and, more particularly, to a combination of planar and multi-planar thin-film transistors (TFTs) and a method for simultaneously fabricating planar and multi-planar TFTs.
2. Description of the Related Art
The size of TFTs formed in liquid crystal display (LCD) processes are limited by the resolution of large panel photolithography tools. Currently, the resolution of feature sizes is about 0.5 microns (um) and larger. High-speed circuit operation requires a TFT capable of high drive current and low parasitic capacitance. These characteristics are obtained by shrinking the device size, especially the transistor channel length. For example, conventional production CMOS technology uses transistor channel lengths of 90 nanometers (nm), and lower, for very high-speed operation.
FIGS. 1A and 1B are a schematic drawing and a plan view, respectively, of a conventional inverter circuit (prior art). The most basic logic element is an inverter, consisting of an N and P channel transistor as shown in FIG. 1A. A common arrangement for fabrication of an inverter circuit uses planar transistors is shown in FIG. 1B. These transistors have a channel length (L) equal to 0.8 microns. Note that the width of the P channel device is larger than the N channel device because of the higher drive current of N channel transistors. In most cases the P/N width ratio is about 2.
The above-mentioned Related Applications disclose two different types of multi-planar TFTs (MP-TFTs). A vertical TFT (V-TFT) has one source/drain (S/D) region in the same plane as the gate, as is conventional with a planar TFT (P-TFT), a second S/D region in a second plane overlying the gate, and a very short channel length formed along the sidewalls between the two S/D regions. A dual-gate TFT (DG-TFT) forms a bottom gate underlying the two S/D regions and channel region, and a top gate overlying the channel regions. The dual-gate control mechanism permits the threshold voltage to be more precisely controlled.
These devices address specific integration needs for next generation advanced displays. For example, advanced displays require the use of high-speed circuit functions involving image processing, voice recognition, wireless communication that can be directly (i.e. monolithically) integrated onto the substrate of the display itself. Monolithic integration becomes particularly appealing for the fabrication of novel display products featuring ultra-light, low-power consumption, and flexible characteristics.
Although these novel functions require novel device structures, certain basic display functions, such as pixel switching and power circuit architectures, can be best served by conventional device structures. For example, deep-sub-um P-TFT devices are known to be reliable when operated under high drain or gate voltages. Therefore, the co-integration of P-TFTs with MP-TFTs is desirable. This co-integration, ideally, can be made to occur without the addition of masking steps, which increase the manufacturing costs of display panels.
It would be advantageous if CMOS circuits in general and, more specifically, liquid crystal displays (LCDs) could be built using the two above-mentioned MP-TFTs, fabricated simultaneous with P-TFTs.
It would be advantageous if the above-mentioned P-TFTs and MP-TFTs could be fabricated using conventional CMOS processes.